MAX19710EVKIT+【PDF 9/21 页】EVAL KIT FOR MAX19710

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MAX19710–MAX19713 Evaluation

Kits/Evaluation Systems

Reference

The MAX19710–MAX19713 feature two reference oper-

ation modes. The EV kits can be configured to use

either the internal (1.024V) reference or an external

user-supplied reference applied at the REFIN pad. The

AFEs generate the REFP and REFN voltages from the

selected reference voltage (refer to the MAX19710,

MAX19711, MAX19712, and MAX19713 data sheets for

more details). Measure the REFP and REFN voltages at

TP1 and TP2, respectively. Jumper JU2 controls the ref-

erence mode. See Table 2 for jumper configurations.

Table 2. Reference Shunt Settings (JU2)

SHUNT POSITION DESCRIPTION

Digital Data Headers

The MAX19710–MAX19713 EV kits feature two 10-bit

parallel data buses used for full-duplex operation. The two

data buses are accessed on the EV kit through header

connectors J2 (Rx ADC bus) and J3 (Tx DAC bus).

Digital Data Bit Locations

Driver U2 buffers the digital outputs of the Rx ADC. This

driver is able to drive large capacitive loads, which may

be present at the logic analyzer connection. The out-

puts of the buffer are connected to a 40-pin header

(J2). The 20-pin header (J3) is used to connect to the

digital input of the Tx DAC. See Table 3 for bit locations

on headers J2 and J3.

Installed*

Not installed

*Default configuration.

Internal reference mode.

External reference mode.

Apply an external reference voltage to

the REFIN pad.

Configuring the Low-Speed DAC Buffers

The MAX19710–MAX19713 EV kits feature on-board

configurable buffers. By default, these buffers are config-

ured for unity gain. Measure the buffered voltage at the

BDAC1, BDAC2, and BDAC3 pads. Measure the

unbuffered voltage at the DAC1, DAC2, and DAC3 pads.

Table 3. Digital Data Bit Locations

SIGNAL

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

AD8

AD9

CLKOUT

BDOUT

LOCATION

J2-37

J2-35

J2-33

J2-31

J2-29

J2-27

J2-25

J2-23

J2-21

J2-19

J2-3

J2-9

TYPE

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

DESCRIPTION

Data Bit 0 (LSB)

Data Bit 1

Data Bit 2

Data Bit 3

Data Bit 4

Data Bit 5

Data Bit 6

Data Bit 7

Data Bit 8

Data Bit 9 (MSB)

Incoming Clock Signal

Aux-ADC Digital Output

(requires R38 short)

DA0 J3-19 Input

DA1 J3-17 Input

DA2 J3-15 Input

DA3 J3-13 Input

DA4 J3-11 Input

DA5 J3-9 Input

DA6 J3-7 Input

DA7 J3-5 Input

DA8 J3-3 Input

DA9 J3-1 Input

Note: Pins 1, 5, 7, 11, 13, 15, 17, and 39 of J2 are open. All other pins are connected to OGND.

Data Bit 0 (LSB)

Data Bit 1

Data Bit 2

Data Bit 3

Data Bit 4

Data Bit 5

Data Bit 6

Data Bit 7

Data Bit 8

Data Bit 9 (MSB)

_______________________________________________________________________________________

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